B.S. Computer Engineering, Summa Cum Laude
North Carolina State University, Raleigh, NC

M.S. Electrical Engineering, Thesis
North Carolina State University, Raleigh, NC

J.D. Intellectual Property Law, Cum Laude, Lewis & Clark Law Review
Lewis & Clark Law School, Portland, OR

Assistant

Usman Mughal

Usman is a Partner with the firm. Usman’s practice focuses on patent prosecution of electrical, computer, and software-related inventions. He also provides litigation support for non-infringement and validity opinions of third-party patents.

He has a rich and broad practical background in technologies such as: telecommunications, semiconductors, thermal sensors, high speed I/Os, PLLs, DLLs, amplifiers, platform design, Verilog based design validation, CAD tool design, wireless, antennas, microwave circuits, and software design including object-oriented programming.

Usman is active in the local community. He co-founded a safety-net non-profit clinic in SW Portland called South West Community Health Center. The Center provides health care services to uninsured and underinsured clients. Usman is also active in the local legal community. He served as the President for the Oregon Patent Law Association (OPLA) and chaired a 3-day CLE conference at Salishan Resort in Oregon.

Usman started practicing patent law after working at Intel Corporation in Hillsboro Oregon as a Design Engineer for nine years in microprocessor design. He holds over ten U.S. Patents and has co-authored over fifteen technical papers. Before joining Intel, he interned at Cadence Design System in Cary, North Carolina, and Nortel Networks in Durham, North Carolina.

Patents

I/O Circuit Patents:

“Apparatus and Method for Dynamic On-Die Termination in an Open-Drain Bus Architecture System,” Inventors: Usman A. Mughal, Razi Uddin, Chee how Lim et al. Patent#: 6,411,122 Issued: 06/25/2002.

  • This method saved up to 50% of dynamic power at the driver side of AGTL buffer.  It was the first time Intel used this novel technique to save power for mobile CPUs while preserving signal integrity of the bus.

“Apparatus and Method to Provide a Single Reference Component for Multiple Circuit Compensation using Digital Impedance Code Shifting,” Inventors: Usman A. Mughal, et al, Patent#: 6,545,522, Issued: 04/08/2003.

  • This method used a single package pin as reference for termination resistance, I/O slew rate, and pull-down resistance compensation.  It saved Intel millions of dollars of package pin cost.

“Apparatus and Method to use a Single Reference Component in a Master-Slave Configuration for Multiple Circuit Compensation,” Inventors: Usman A, Mughal, Gregory Taylor, et al, Patent#: 6,535,047, Issued: 03/18/2003.

  • This method used a single package pin as reference for compensating many circuits.  The circuit technique used a master-slave configuration.  It saved Intel millions of dollars of package pin cost.

“Circuit Compensation Technique,” Inventors: C.H. Lim and Usman A. Mughal, Patent#: 6,509,780, Issued: 01/21/2003.

  • An intelligent compensation scheme that minimized glitches in the actual circuits that used compensation information.  By removing these glitches, timing margin on the I/O improved thus allowing them to run faster.

“Apparatus and Method for Linear On-Die Termination in an Open Drain Bus Architecture System,” Inventors: Raghu Raman, Usman A. Mughal, et al, Patent#: 6,424,170, Issued: 07/23/2002.

  • A novel termination circuit for I/Os that provided linear resistance in the operating range of 45-65 Ohms.  The design also protected transistor oxide, thus its longevity, by reducing stress across gate-drain voltages.
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“Apparatus and Method to use a Single Reference Component in a Master-Slave Configuration for Multiple Circuit Compensation,” Inventors: Usman A, Mughal, Gregory Taylor, et al, Patent#: 6,717,455, Issued: 04/06/2004.

  • Using a single package pin as reference for termination resistance, multiple I/O driver circuits were compensated by using one compensated circuit as reference.  Saved Intel millions of dollars of package pin cost.

“Apparatus and Method to Provide a Single Reference Component for Multiple Circuit Compensation using Digital Impedance Code Shifting,” Inventors: Usman A. Mughal, et al, Patent#: 6,756,810, Issued: 06/29/2004.

  • By shifting compensation codes, impedances were changed for different I/O terminations.  The method used the same reference resistor for uni-processor and dual-processor I/O termination resistance.  Saved Intel money.

Platform Patent: 

“Bus Termination Scheme for Flexible Uni-Processor and Dual Processor Platforms,” Inventors: V. Ramachandran, Usman A. Mughal, and Chee How Lim, Patent#: 6,522,165, Issued: 02/18/2003.

  • A novel termination scheme using a single platform topology for Uni and Dual-processor systems thus saving an extra motherboard design.  The design preserved system signal integrity of a Uni-processor system.

PLL and DLL Circuit Patents:

“Variable Lock Window for a Phase Locked Loop,” Inventors: K. L. Wong, Usman A. Mughal, et al. Patent#: 6,614,317 Issued: 09/02/2003.

  • Solved the problem of losing PLL lock signal at low operating frequencies when jitter can be higher.  The circuit generated a wide lock window at low frequency and a narrow lock window at high frequency.

“Variable Slope Adjustment Circuit for Digital Interpolators,” Inventors: Usman A. Mughal and Keng L. Wong. Patent#: 7,154,320: Issued: 12/27/2006.

  • A novel circuit design technique to improve operation of digital phase blenders.  The circuit adjusted the input slopes to the phase blender to generate uniformly spaced interpolated output signals.  Vital for DLLs.

Thermal Management Circuit Patent:

“Accurate on-die temperature measurement using remote sensing,” Inventors: David Duarte, Usman A. Mughal, et al., Patent#: 7,512,514: Issued: 03/31/2009.

  • Remote thermal sensing technique that improves sensing accuracy by calibrating errors generated by self-heating of the silicon.  Vital for power management systems on CPUs.

Publications

External: IEEE – AP, MTT, EPEP, CICC; MURI, ITC, ISTFA, EDFAS, ISLPED:  

Microwave – CAD:

Abdulla, M.N., Mughal, U.A., Steer, M.B., “Network characterization of a finite array of folded-slot antennas for spatial power combining application,” Antennas and Propagation Society, 1999. IEEE International Symp. 1999, Vol. 4, 1999.

Abdulla, M.N., Mughal, U.A., H.S. Tsai, Steer, M.B, et al., “A full-wave system simulation of a folded-slot spatial power combining amplifier array,” Microwave Symposium Digest, 1999 IEEE MTT-S International, Vol. 2, 1999.

Steer, M.B., Harvey, J.F., Mink, J.W, Mughal, U.A., et al, “Global modeling of spatially distributed microwave and millimeter-wave systems,” Microwave Theory and Techniques, IEEE Transactions, Vol. 47 Issue: 6 Part: 2, June 1999.

Mughal, U.A., “Hierarchical approach to global modeling of active antenna arrays,” M.S. Thesis North Carolina State University, 1999.

Christoffersen, C.E., Mughal, U.A., and Steer, M.B, “Object oriented microwave circuit simulator,” Int. J. on RF and Microwave Computer Aided Engineering, Vol. 10, Issue 3, 2000, pp. 164–182. (MURI).

Mixed Signal Circuit Validation:

Y. C. Pan, U. A. Mughal, et al, “Mixed signal validation of the Intel Pentium 4 microprocessor power-up sequence,” Proc. IEEE 12th Topical Meeting on EPEP, Princeton, NJ, pp. 163-166, Oct. 2003.

Analog Circuit Design:

B. Mauck, V. Ravichandran, and U. Mughal, “A Design-for-Test Technique for Parametric Analysis of SRAM: On-Die Low Yield Analysis,” International Test Conference (ITC) 2004.

B. M. Mauck, V. Ravichandran, and U. A. Mughal, “On-Die Parametric Analysis of SRAM,” 30th International Symposium for Testing and Failure Analysis (ISTFA), 2004.

B. Mauck, V. Ravichandran, and U. Mughal, “On-Die LYA,” Electronic Device Failure Analysis Society (EDFAS), Vol. 9 No. 3, pp. 22-29, 2005.

D. Duarte, U. Mughal, et al, “Temperature Sensor Design in a High Volume Manufacturing 65nm CMOS Digital Process,” IEEE Custom Integrated Circuits Conference (CICC), Sept. 2007.

D. Duarte, U. Mughal, et al, “Advanced thermal sensing circuit and test techniques used in a high performance 65nm processor,” International Symposium on Low Power Electronics and Design (ISLPED) 2007.

Internal: Intel DTTC:

Mixed Signal Circuit Validation:

Y.C. Pan, S. Kim, Usman A. Mughal, et al, “Mixed Signal Validation of Prescott Microprocessor Power-Up Sequence”, Intel Design and Test Technology Conference (DTTC), 2003.

Y. Pan, R. Cohen, U. Mughal, et al, “Analog Mixed Signal Validation of Special Circuits in Cedar Mill Microprocessor,” Special Validation Topics, Intel Design and Test Technology Conference (DTTC), 2004.

Analog Circuit Design:

B. Mauck, V. Ravichandran, and U. Mughal, “A Design for Test Technique for Parametric Analysis of SRAM: On-die LYA,” Memory and IO DFT, Intel Design and Test Technology Conference (DTTC), 2004.

D. Duarte, G. Geannopoulos, U. Mughal, and K. Wong, “Novel P1264 Thermal Sensor with Linearity and Range Compensation,” Intel Design and Test Technology Conference (DTTC), 2005.

D. Duarte, G. Geannopoulos, U. Mughal, C. Deng, and K. Wong, “Novel Circuits and Test Techniques for High Accuracy HVM Thermal Sensor Designs,” Intel Design and Test Technology Conference (DTTC), 2006.

Bar Admissions

Oregon State Bar

Patent Bar

USPTO Registration # 62,887

Awards